A Novel Interconnect Structure for Elmore Delay Model with Resistance-Capacitance-Conductance Scheme
نویسندگان
چکیده
In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the interconnect delay estimates can be improved by deploying the conductance effect. The simulation results shows the proposed interconnect scheme performance is better than the existing in terms of delay, power and the figure of merit. The performance analysis depicts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.
منابع مشابه
RC on-chip interconnect Performance revisited
The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in submicrometer domain due to the inability of a so simple model...
متن کاملSimultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By ...
متن کاملRobust Elmore Delay Models Suitable for Full Chip Timing Veri cation of a 600MHz CMOS Microprocessor
In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50% point delay of CMOS circuits in a static timing veri er. Elmore delays comp...
متن کاملDelay Metric for On-chip Rlcg Coupled Interconnects for Ramp Input
In this paper we have put forward an analytical model which can could accurately compute the on chip interconnect delay using distributed RLCG segments. With the increasing level of on chip integration the interconnect delay has acquired prominence for performance driven layout synthesis. Also in higher frequency range of the order of GHz , the effect of shunt conductance and inductance cannot ...
متن کاملClosed form Delay Model for on-Chip VLSIRLCG Interconnects for Ramp Input for Different Damping Conditions
Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Sev...
متن کامل